SPRZ193T January 2003 – December 2023 SM320F2812 , SM320F2812-EP , SMJ320F2812 , TMS320F2810 , TMS320F2810-Q1 , TMS320F2811 , TMS320F2811-Q1 , TMS320F2812 , TMS320F2812-Q1
XINTF: XBANK Does Not Properly Extend an Access
0, A, B, C, D, E, F and G
When XTIMCLK is not equal to SYSCLKOUT, the XBANK logic may not properly delay a pending access. This occurs for some combinations of XINTF zone wait states and XBANK delay cycles. There are two cases when this occurs.
Case 1: When XTIMCLK = 1/2 SYSCLKOUT and XCLKOUT = XTIMCLK
A pending access may not be delayed by the XBANK logic if either:
Where WLEAD, WACTIVE, WTRAIL, RLEAD, RACTIVE, RTRAIL are defined as shown in Table 5-2.
| X2TIMING = 0 | X2TIMING = 1 | |
|---|---|---|
| WLEAD | XTIMING x [XWRLEAD] | XTIMING x [XWRLEAD] x 2 |
| WACTIVE | XTIMING x [XWRACTIVE] + 1 | XTIMING x [XWRACTIVE] x 2 + 1 |
| WTRAIL | XTIMING x [XWRTRAIL] | XTIMING x [XWRTRAIL] x 2 |
| RLEAD | XTIMING x [XRDLEAD] | XTIMING x [XRDLEAD] x 2 |
| RACTIVE | XTIMING x [XRDACTIVE] + 1 | XTIMING x [XRDACTIVE] x 2 + 1 |
| RTRAIL | XTIMING x [XRDTRAIL] | XTIMING x [XRDTRAIL] x 2 |
In Table 5-2, XTIMINGx refers to the XTIMING register for Zone x. When XBANK delay cycles are added between two accesses, Zone x refers to the first zone in the sequence. For example: if XBANK[BANK] = 7, then delay cycles will be added to any access into or out of Zone 7. This means:
Thus, the timing of any zone involved in bank switching must be considered.
Case 2) When XTIMCLK = 1/2 SYSCLKOUT and XCLKOUT = 1/2 XTIMCLK:
A pending access may not be delayed properly by the XBANK logic if XBANK[BCYC] = 4 or XBANK[BCYC] = 6.
Case 1) If XTIMCLK = 1/2 SYSCLKOUT and XCLKOUT = XTIMCLK, then select:
When XBANK delay cycles are added between two accesses, the timing restriction applies to the first zone accessed as described earlier. The timing of any zone involved in bank switching must be considered.
Table 5-3 shows examples of valid XBANK[BCYC] selections. This list is not exhaustive.
| XWRLEAD XRDLEAD | WRACTIVE XRDACTIVE | XWRTRAIL XRDTRAIL | X2TIMING | WLEAD + WACTIVE + WTRAIL | Choose XBANK[BCYC] |
|---|---|---|---|---|---|
| 1 | 2 | 1 | 0 | 5 | < 5 |
| 1 | 3 | 1 | 0 | 6 | < 6 |
| 2 | 3 | 1 | 0 | 7 | < 7 |
| 1 | 0 | 1 | 1 | 3 | < 3 |
| 1 | 1 | 0 | 1 | 5 | < 5 |
| 1 | 1 | 1 | 1 | 7 | < 7 |
Case 2: If XTIMCLK = 1/2 SYSCLKOUT and XCLKOUT = 1/2 XTIMCLK, then select: