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SPRZ193T January 2003 – December 2023 SM320F2812 , SM320F2812-EP , SMJ320F2812 , TMS320F2810 , TMS320F2810-Q1 , TMS320F2811 , TMS320F2811-Q1 , TMS320F2812 , TMS320F2812-Q1

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1Introduction
2Device and Development Tool Support Nomenclature
3Device Markings
4Usage Notes and Known Design Exceptions to Functional Specifications
1. 4.1 Usage Notes
  1. 4.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Usage Note
5Known Design Exceptions to Functional Specifications
1. Advisory
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6Documentation Support
7Trademarks
8Revision History

Advisory

ADC: Sequencer Reset While Dual Sequencers Are Running

Revision(s) Affected

0, A, B, C, D, E, F and G

Details

In the TMS320F2812/TMS320F2811/TMS320F2810 on-chip ADC, there are two sequencers for performing ADC conversions; SEQ1 and SEQ2. If one of the sequencers is reset while the other sequencer is running, it will result in the running sequencer never completing its current sequence. The sequencer busy bit (bit 3/bit 2 in ADCST register) for the sequencer will remain active and an “End-of-sequence (EOS)” interrupt for the running sequencer will never be generated. For example, if SEQ1 is reset while SEQ2 is performing a sequence, then SEQ2 will never complete.

Workaround(s)

If dual sequencers are enabled, then the software handling the ADC module should make sure that SEQ1 BSY/ SEQ2 BSY bits are not set before performing a reset of either sequencer.