SPRZ272N September 2007 – April 2022 SM320F28335-EP , SM320F28335-HT , TMS320F28232 , TMS320F28232-Q1 , TMS320F28234 , TMS320F28234-Q1 , TMS320F28235 , TMS320F28235-Q1 , TMS320F28332 , TMS320F28333 , TMS320F28334 , TMS320F28335 , TMS320F28335-Q1
NUMBER | TITLE | SILICON REVISION(S) AFFECTED | |
---|---|---|---|
0 | A | ||
Section 3.1.1 | PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear | Yes | Yes |
Section 3.1.2 | Caution While Using Nested Interrupts | Yes | Yes |
Section 3.1.3 | Watchdog: Watchdog Issues Reset After Bad Key is Written | Yes | Yes |
Section 3.1.4 | McBSP: XRDY Bit can Hold the Not-Ready Status (0) if New Data is Written to the DX1 Register Without First Verifying if the XRDY Bit is in its Ready State (1) | Yes | Yes |
Section 3.1.5 | Maximum Flash Program Time and Erase Time in Revision O of the TMS320F2833x, TMS320F2823x Real-Time Microcontrollers Data Sheet | Yes |