米6体育平台手机版

SPRZ272N September 2007 – April 2022 SM320F28335-EP , SM320F28335-HT , TMS320F28232 , TMS320F28232-Q1 , TMS320F28234 , TMS320F28234-Q1 , TMS320F28235 , TMS320F28235-Q1 , TMS320F28332 , TMS320F28333 , TMS320F28334 , TMS320F28335 , TMS320F28335-Q1

1Usage Notes and Advisories Matrices
1. 1.1 Usage Notes Matrix
2. 1.2 Advisories Matrix
2Nomenclature, Package Symbolization, and Revision Identification
3Silicon Revision A Usage Notes and Advisories
1. 3.1 Silicon Revision A Usage Notes
2. 3.2 Silicon Revision A Advisories
  1. Advisory
  2. Advisory
  3. Advisory
  4. Advisory
  5. Advisory
  6. Advisory
  7. Advisory
  8. Advisory
  9. Advisory
  10. Advisory
  11. Advisory
  12. Advisory
  13. Advisory
4Silicon Revision 0 Usage Notes and Advisories
1. 4.1 Silicon Revision 0 Usage Notes
2. 4.2 Silicon Revision 0 Advisories
  1. Advisory
  2. Advisory
  3. Advisory
5Documentation Support
6Trademarks
7Revision History

Advisory

Memory: Possible Incorrect Operation of XINTF Module After Power Up

Revision(s) Affected

0, A

Details

The XINTF module may not get reset properly upon power up. When this happens, accesses to XINTF addresses may cause the CPU to hang. This issue occurs only upon power up. It does not happen for other resets such as a reset initiated by the watchdog or an external (warm) reset using the XRS pin.

Workaround(s)

After coming out of reset, software should force a watchdog (WD) reset if WDFLAG = 0 in the WDCR register. WDFLAG = 0 implies that an external reset occurred, for example, a power-on reset. After exiting the WD reset, WDFLAG will be 1. In this case, software should clear the WDFLAG bit before continuing normal code execution. This issue affects only the XINTF module. Note that the code should sample the WDFLAG bit only after a delay of 8192 SYSCLKOUT cycles from the time reset is deasserted.