Revision(s) Affected

0

Details

Figure 4-1 shows the behavior of zone chip select signals and XA0/ XWE1 for back-to-back accesses between zones configured for different data bus widths.

For the x32-bit zone (XTIMINGx[XSIZE] = 1) the A0/ XWE1 signal is the write enable XWE1. For the x16-bit zone (XTIMINGx[XSIZE] = 3) the A0/ XWE1 signal is address line A0.

Design simulation data indicates the delta between XZCS (x32) high and XA0/ XWE1 low can be as small as 200 ps.

Design simulation data indicates XA0/ XWE1 can stay low for as long as 1 ns after XZCS (x32) goes low.

Figure 4-1 Behavior of Zone Chip Select Signals and XA0/ XWE1

When A0/ XWE1 changes functionality, the x32 zone chip select signal ( XZCS x32) changes state. Depending on the board design and peripherals attached to the XINTF, it is possible that an external memory or peripheral on the x32 zone may respond to A0/ XWE1 switching as a write access. If this happens, a rogue write to the x32 zone can occur.

Workaround(s)

1. If all zones are configured for x16 operation, then no action is required.
2. If all zones are configured for x32 operation, then XA0/ XWE1 will switch from XA0 to XWE1 on the first access. After the first access, the XA0/ XWE1 pin will remain as XWE1. To keep external devices from responding to the XA0/ XWE1 change, follow these steps when configuring the XINTF module:
   1. Enable the clock to the XINTF module.
   2. Configure the data-width and timing of the XINTF zones.
   3. Configure the zone chip select pins as GPIO inputs for the next step. This is the default behavior after reset.
   4. Perform a dummy read from a x32 XINTF zone. This read will force XA0/ XWE1 to behave as XWE1. Since the zone chip selects are configured as GPIO inputs, the external devices will not respond to XA0/ XWE1 switching to XWE1. After the first read, XA0/ XWE1 will continue to behave as XWE1.
   5. Configure the GPIO MUX registers for XINTF operation.
3. Use external logic to delay the falling edge of the x32 zone chip select signal and the falling edge of the XWE1 signal as shown in Figure 4-2. With the delay the x32 zone chip select sees the XWE1 signal high at the critical points.

The timing configuration of the x32 zone must account for the additional delay. The zone chip select delay may require additional lead time. The XWE1 delay enable may require additional active write time. In addition, specify at least 1 trail cycle for writes to the x32 zone.

Delayed falling edge of zone chip select for x32 zone.

Delayed falling edge of XWE1. The x16 zone will not see this delay.

Figure 4-2 Behavior After Application of Delay

The delay can be created by using 74LVC32 quad OR gates or similar logic to create a delay line as shown in Figure 4-3.

Figure 4-3 Example Delay Line Circuit

This has been fixed in Rev A silicon. The external delay logic is no longer required to avoid this issue in Rev A. The behavior of the XA0/ XWE1 signal has been modified such that it goes high during inactive cycles. Use the XBANK feature to force inactive cycles between back-to-back zone accesses. See the External Interface (XINTF) chapter of the TMS320x2833x, TMS320x2823x Real-Time Microcontrollers Technical Reference Manual for more information.