米6体育平台手机版

SPRZ272N September 2007 – April 2022 SM320F28335-EP , SM320F28335-HT , TMS320F28232 , TMS320F28232-Q1 , TMS320F28234 , TMS320F28234-Q1 , TMS320F28235 , TMS320F28235-Q1 , TMS320F28332 , TMS320F28333 , TMS320F28334 , TMS320F28335 , TMS320F28335-Q1

1Usage Notes and Advisories Matrices
1. 1.1 Usage Notes Matrix
2. 1.2 Advisories Matrix
2Nomenclature, Package Symbolization, and Revision Identification
3Silicon Revision A Usage Notes and Advisories
1. 3.1 Silicon Revision A Usage Notes
2. 3.2 Silicon Revision A Advisories
  1. Advisory
  2. Advisory
  3. Advisory
  4. Advisory
  5. Advisory
  6. Advisory
  7. Advisory
  8. Advisory
  9. Advisory
  10. Advisory
  11. Advisory
  12. Advisory
  13. Advisory
4Silicon Revision 0 Usage Notes and Advisories
1. 4.1 Silicon Revision 0 Usage Notes
2. 4.2 Silicon Revision 0 Advisories
  1. Advisory
  2. Advisory
  3. Advisory
5Documentation Support
6Trademarks
7Revision History

Advisory

Memory: Prefetching Beyond Valid Memory

Revision(s) Affected

0, A

Details

The C28x CPU prefetches instructions beyond those currently active in its pipeline. If the prefetch occurs past the end of valid memory, then the CPU may receive an invalid opcode.

Workaround

The prefetch queue is 8 x16 words in depth. Therefore, code should not come within 8 words of the end of valid memory. This restriction applies to all memory regions and all memory types (flash, OTP, SARAM, XINTF) on the device. Prefetching across the boundary between two valid memory blocks is all right.

Example 1: M1 ends at address 0x7FF and is not followed by another memory block. Code in M1 should be stored no farther than address 0x7F7. Addresses 0x7F8–0x7FF should not be used for code.

Example 2: M0 ends at address 0x3FF and valid memory (M1) follows it. Code in M0 can be stored up to and including address 0x3FF. Code can also cross into M1 up to and including address 0x7F7.