SPRZ272N September   2007  – April 2022 SM320F28335-EP , SM320F28335-HT , TMS320F28232 , TMS320F28232-Q1 , TMS320F28234 , TMS320F28234-Q1 , TMS320F28235 , TMS320F28235-Q1 , TMS320F28332 , TMS320F28333 , TMS320F28334 , TMS320F28335 , TMS320F28335-Q1

 

  1. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  2. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
    4. 2.4 Silicon Change Overview
  3. 3Silicon Revision A Usage Notes and Advisories
    1. 3.1 Silicon Revision A Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Usage Note
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 Watchdog: Watchdog Issues Reset After Bad Key is Written
      4. 3.1.4 McBSP: XRDY Bit can Hold the Not-Ready Status (0) if New Data is Written to the DX1 Register Without First Verifying if the XRDY Bit is in its Ready State (1)
      5. 3.1.5 Maximum Flash Program Time and Erase Time in Revision O of the TMS320F2833x, TMS320F2823x Real-Time Microcontrollers Data Sheet
    2. 3.2 Silicon Revision A Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
  4. 4Silicon Revision 0 Usage Notes and Advisories
    1. 4.1 Silicon Revision 0 Usage Notes
    2. 4.2 Silicon Revision 0 Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
  5. 5Documentation Support
  6. 6Trademarks
  7. 7Revision History

Advisory

eQEP: Missed First Index Event

Revision(s) Affected

A

Details

If the first index event edge at the QEPI input occurs at any time from one system clock cycle before the corresponding QEPA/QEPB edge to two system clock cycles after the corresponding QEPA/QEP edge, then the eQEP module may miss this index event. This can result in the following behavior:

  • QPOSCNT will not be reset on the first index event if QEPCTL[PCRM] = 00b or 10b (position counter reset on an index event or position counter reset on the first index event).
  • The first index event marker flag (QEPSTS[FIMF]) will not be set.

Workaround(s)

Reliable operation is achieved by delaying the index signal such that the QEPI event edge occurs at least two system clock cycles after the corresponding QEPA/QEPB signal edge. For cases where the encoder may impart a negative delay (td) to the QEPI signal with respect to the corresponding QEPA/QEPB signal (that is, QEPI edge occurs before the corresponding QEPA/QEPB edge), the QEPI signal should be delayed by an amount greater than "td + 2*SYSCLKOUT".