SPRZ272N September   2007  – April 2022 SM320F28335-EP , SM320F28335-HT , TMS320F28232 , TMS320F28232-Q1 , TMS320F28234 , TMS320F28234-Q1 , TMS320F28235 , TMS320F28235-Q1 , TMS320F28332 , TMS320F28333 , TMS320F28334 , TMS320F28335 , TMS320F28335-Q1

 

  1. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  2. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
    4. 2.4 Silicon Change Overview
  3. 3Silicon Revision A Usage Notes and Advisories
    1. 3.1 Silicon Revision A Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Usage Note
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 Watchdog: Watchdog Issues Reset After Bad Key is Written
      4. 3.1.4 McBSP: XRDY Bit can Hold the Not-Ready Status (0) if New Data is Written to the DX1 Register Without First Verifying if the XRDY Bit is in its Ready State (1)
      5. 3.1.5 Maximum Flash Program Time and Erase Time in Revision O of the TMS320F2833x, TMS320F2823x Real-Time Microcontrollers Data Sheet
    2. 3.2 Silicon Revision A Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
  4. 4Silicon Revision 0 Usage Notes and Advisories
    1. 4.1 Silicon Revision 0 Usage Notes
    2. 4.2 Silicon Revision 0 Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
  5. 5Documentation Support
  6. 6Trademarks
  7. 7Revision History

Advisory

eQEP: Position Counter Incorrectly Reset on Direction Change During Index

Revision(s) Affected

0, A

Details

While using the PCRM = 0 configuration, if the direction change occurs when the index input is active, the position counter (QPOSCNT) could be reset erroneously, resulting in an unexpected change in the counter value. This could result in a change of up to ±4 counts from the expected value of the position counter and lead to unexpected subsequent setting of the error flags.

While using the PCRM = 0 configuration [that is, Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)], if the index event occurs during the forward movement, then the position counter is reset to 0 on the next eQEP clock. If the index event occurs during the reverse movement, then the position counter is reset to the value in the QPOSMAX register on the next eQEP clock. The eQEP peripheral records the occurrence of the first index marker (QEPSTS[FIMF]) and direction on the first index event marker (QEPSTS[FIDF]) in QEPSTS registers. It also remembers the quadrature edge on the first index marker so that same relative quadrature transition is used for index event reset operation.

If the direction change occurs while the index pulse is active, the module would still continue to look for the relative quadrature transition for performing the position counter reset. This results in an unexpected change in the position counter value.

Workaround(s)

Do not use the PCRM = 0 configuration if the direction change could occur while the index is active and the resultant change of the position counter value could affect the application.

Other options for performing position counter reset, if appropriate for the application [such as Index Event Initialization (IEI)], do not have this issue.