Revision(s) Affected

0, A, B

Details

CPU reads of bits 8, 9, and 10 of the MMEMCFG register in the CLA module will always return a zero. Writes to these bits will work as expected.

Workaround(s)

None. To modify the bits of this register, a single write to the entire register with the complete configuration should be performed. Read-Modify-Write should not be used as any Read-Modify-Write operation to the register will read a zero for bits 8, 9, and 10 and can write back a zero to those bits and thus modifying these bits unintentionally. An example is shown below:

#define CLA_PROG_ENABLE      0x0001 
#define CLARAM0_ENABLE       0x0010 
#define CLARAM1_ENABLE       0x0020 
#define CLARAM2_ENABLE       0x0040 
#define CLA_RAM0CPUE         0x0100 
#define CLA_RAM1CPUE         0x0200 
#define CLA_RAM1CPUE         0x0400 
Cla1Regs.MMEMCFG.all  = CLA_PROG_ENABLE1|  CLARAM0_ENABLE|CLARAM1_ENABLE|CLARAM2_ENABLE|CLA_RAM1CPUE;