SPRZ397K November 2012 – September 2024 TDA2EG-17 , TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2SA , TDA2SG , TDA2SX
DELAYMODE Mechanism Not Selecting Proper Delay for Some IP Modes
High
IO timings are not met for some IPs and IP modes, and specific configuration of the DELAYMODE and SLEW configurations in the pad control registers (control module) are required for them.
If these modes are used, the SoC should only be used under nominal conditions (for example, room temp/lab/software development), not for production testing.
SR 1.0
TDA2x: 1.0
DRA75x, DRA74x: 1.0
AM572x: 1.0