CRITICALITY

Medium

DESCRIPTION

If AVS voltage change on CORE_VD domain is used, there is a recalibration sequence which is required to ensure that IO timings meet timings per the Data Manual (software sequence to be included in TRM). This recalibration sequence is not reliable, and must be avoided. Therefore, IO timings may not be met after any CORE_VD voltage change. If AVS is not used on CORE_VD, the IO timings are fine since there is an automatic hardware calibration that happens one time directly after POR.

WORKAROUND

Keep the CORE_VD at the initial boot voltage. Power consumption may be slightly higher than optimal since AVS voltage is not used.

REVISIONS IMPACTED

SR 1.0

TDA2x: 1.0

DRA75x, DRA74x: 1.0

AM572x: 1.0