米6体育平台手机版

SPRZ397K November 2012 – September 2024 TDA2EG-17 , TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2SA , TDA2SG , TDA2SX

1
1Introduction
1. Related Documentation
2. Trademarks
3. Modules Impacted
2Silicon Advisories
1. Revisions SR 2.0, 1.1, 1.0 - Advisories List
2. i202
3. i378
4. i631
5. i694
6. i698
7. i699
8. i727
9. i729
10. i734
11. i767
12. i782
13. i783
14. i802
15. i803
16. i807
17. i808
18. i809
19. i810
20. i813
21. i814
22. i815
23. i818
24. i819
25. i820
26. i824
27. i826
28. i829
29. i834
30. i837
31. i840
32. i841
33. i842
34. i843
35. i847
36. i849
37. i852
38. i854
39. i855
40. i856
41. i859
42. i861
43. i862
44. i863
45. i868
46. i869
47. i870
48. i871
49. i872
50. i874
51. i875
52. i878
53. i879
54. i880
55. i882
56. i883
57. i884
58. i887
59. i889
60. i890
61. i893
62. i895
63. i896
64. i897
65. i898
66. i899
67. i900
68. i901
69. i903
70. i916
71. i927
72. i929
73. i930
74. i932
75. i933
76. i936
77. i940
78. i2446
3Silicon Limitations
1. Revisions SR 2.0, 1.1, 1.0 - Limitations List
2. i596
3. i641
4. i833
5. i838
6. i844
7. i845
8. i848
9. i850
10. i851
11. i853
12. i857
13. i858
14. i876
15. i877
16. i892
17. i909
4Silicon Cautions
1. Revisions SR 2.0, 1.1, 1.0 - Cautions List
2. i781
3. 4.1 106
4. i827
5. i832
6. i836
7. i839
8. i864
9. i885
10. i886
11. i912
12. i926
13. i931
14. i935
5Revision History

i378

sDMA Channel Is Not Disabled after a Transaction Error

CRITICALITY

Medium

DESCRIPTION

In case of destination synchronized transfer on the write port (or source sync with SDMA.DMA4_CCRi[25] BUFFERING_DISABLE = 1), if a transaction error is reported at the last element of the transaction, the channel is not automatically disabled by DMA.

WORKAROUND

Whenever a transaction error is detected on a transaction on the write side of the channel i, software must disable the channel(i) by setting the DMA4_CCRi[7] ENABLE bit to 0.

REVISIONS IMPACTED

SR 2.0, 1.1, 1.0

TDA2x: 2.0, 1.1, 1.0

DRA75x, DRA74x: 2.0, 1.1, 1.0

AM572x: 2.0, 1.1