CRITICALITY

Low

DESCRIPTION

A current path exists between VDD and the high speed analog PHY domain (VDDA_HDMI, VDDA_PCIE, VDDA _SATA, VDDA_USB2/3) during the supply power up and power down sequences.

The device-specific Data Manual requires Core AVS rail (VDD) to power up before the 1.8 V high speed analog PHY domain(s). When this sequence is followed, the high speed analog PHY domain will have a small step-up to a voltage plateau (< 0.5 V) that aligns to the beginning of the VDD ramp-up, and is maintained until the ramp-up of high speed analog PHY rail, as shown in Figure 4-2. Note the leakage value will differ from system to system, but will be less than 500 mV. The leakage voltage in the provided capture is approximately 250 mV.

Figure 4-2 Leakage Voltage

A similar condition exists during supply power down sequence. The high speed analog PHY domain(s) are required to be powered down prior to Core AVS rail (VDD), and may cause a small plateau to exist until Core AVS rail (VDD) is ramped down.

The root cause of the voltage plateau during power-up/down sequencing is related to the parasitic diodes in logic blocks which have multiple power sources. This leakage path is not a reliability concern for this device.

GUIDELINES

None. There is no reliability concern for the device.

REVISIONS IMPACTED

SR 2.0, 1.1, 1.0

TDA2x: 2.0, 1.1, 1.0

DRA75x, DRA74x: 2.0, 1.1, 1.0

AM572x: 2.0, 1.1