CRITICALITY

Low

DESCRIPTION

This Bug can occur only in a channel that is part of a channel chain. If channel chaining is not used, this bug is never seen.

An exact corner case sequence of events must occur. The sequence is:

• The channel is enabled and then aborted*.
• This same channel is now configured as part of a channel chain (it should not be the head of the channel chain).
• The channel is configured as "software synchronized" or "hardware synchronized at destination with prefetch enabled"
• The channel gets enabled through linking.

* Following is the subset of abort conditions for this scenario:

• The channel is disabled in the middle of transaction and channnel is not a drain candidate.
• The channel gets a transaction error on write port but not at the end-of-block transaction.
• The channel gets a read transaction error and is not a drain candidate.

WORKAROUND

The software workaround is to configure DMA4 to be in no-standby or force-standby mode before clearing the PAUSE bit. The DMA4 can be reverted back to smart-standby mode after a certain period (after detecting DMA4_CSRi[15:15] of corresponding channel to be 0 or ensuring DMA4_CSRi[7:7] bit of corresponding channel to be 0. This ensures descriptor load completion or channel termination.

REVISIONS IMPACTED

SR 2.0, 1.1, 1.0

TDA2x: 2.0, 1.1, 1.0

DRA75x, DRA74x: 2.0, 1.1, 1.0

AM572x: 2.0, 1.1