CRITICALITY

Medium

DESCRIPTION

For EMIF 2-bit Error Detection, errors are reported in one of two ways. First, the error is recorded in EMIF control registers and an error interrupt is asserted. Second, the EMIF returns a bus error on the read response status bus along with the read data via the internal bus protocol. The requesting master will receive the error code along with read data.

The EMIF control register and error interrupts correctly record/signal detection of 2-b errors, but the internal bus read response status for a transaction with a 2b error can sometimes be incorrect. The incorrect response occurs due to a logic bug that results in slot21 in the EMIF's read FIFO using the error status of slot20 for its read response status (slot21 and slot20 can contain unrelated transactions from the same or different masters). (Note that there are 32-entries in the read response FIFO that are all used in round-robin order. Slot 20 and 21 are used with equal probability relative to the remaining FIFO slot entries).

Two scenarios are possible:

1. If slot 20 transaction had an error and slot 21 didn't, then the ECC error Interrupt will be triggered and read response status returned for both slot 20 and 21 will indicate an error. Thus slot 21 will indicate a false error.
2. If slot 21 transaction had an error and slot 20 didn't, then the ECC error Interrupt will be triggered and read response status returned for both slot 20 and 21 will indicate no error. Thus the true error status of slot 21 will not be directly communicated back to the requesting master via the read response bus along with the corresponding read data.

Since the read response status for detection of 2-b errors may be incorrect, this may cause some masters to consume erroneous data and/or cause a false exception on valid data. If no 2b error has occurred in the system, there is no impact.

WORKAROUND

Software should rely on EMIF error interrupt (EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS[4] TWOBIT_ECC_ERR_SYS/EMIF_SYSTEM_OCP_INTERRUPT_STATUS[4] TWOBIT_ECC_ERR_SYS=0x1) and error address control registers(EMIF_2B_ECC_ERR_ADDR_LOG[31:0] REG_2B_ECC_ERR_ADDR) to comprehend 2-b ECC errors in the system. It is still advantageous to enable 2b ECC (EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET[4] TWOBIT_ECC_ERR_SYS) versus leaving it off, as statistically many errors would still be properly handled.

REVISIONS IMPACTED

SR 1.0

TDA2x: 1.0

DRA75x, DRA74x: 1.0

AM572x: 1.0