CRITICALITY

Medium

DESCRIPTION

To initialize the parity RAM of DCAN, SW must perform a subsequent write of 0b to the dcan*_raminit_start bit directly after writing the bit to 1b. Due to the bug, the subsequent write to 0b must complete no more than 64 DCAN ICLK periods after the write of 1b. If the time exceeds 64 cycles, the DCAN module could become unusable until the next device reset. A minimum toggle duration of 1 ICLK period is also required.

WORKAROUND

Software should implement the minimum toggle (write 1b then write 0b) to keep the pulse duration less than 64 ICLK cycles while keeping while still meeting the 1 ICLK minimum. The instructions should be executed from internal RAM to minimize latency variance due to internal bus traffic, interrupts, DDR refresh cycles, etc. It is difficult to ensure the less that 64 cycle limits under every system scenario, as it is sensitive to non-deterministic system latencies. Therefore the workaround should be used only for development and not in production.

REVISIONS IMPACTED

SR 1.0

TDA2x: 1.0

DRA75x, DRA74x: 1.0

AM572x: 1.0