CRITICALITY

Medium

DESCRIPTION

MMC1, MMC2 and MMC3 data write operations (single and multiple block writes) fail at speed due to timing issue with CRC response which causes the response to be latched as CRC bad status even if the status from the memory device was good. This limits MMC1 data write operations to 96MHz and MMC2/3 data write operations to 48MHz clock frequency. (See Figure 2-1 for MMCi Maximum Supported Frequencies).

Figure 2-1 MMCi Maximum Supported Frequencies

WORKAROUND

Reduce clock frequency when performing data writes (96MHz for MMC1, 48MHz for MMC2, MMC3). Note, for MMC2, 48MHz DDR mode can be used for bandwidth equivalent to 96MHz. Optionally Increase to full frequency only for read operations. If mixed reads and writes are performed, then the lower frequency must be used.

REVISIONS IMPACTED

SR 1.1, 1.0

TDA2x: 1.1, 1.0

DRA75x, DRA74x: 1.1, 1.0

AM572x: 1.1