米6体育平台手机版

SPRZ408D June 2014 – June 2021 AM4372 , AM4376 , AM4377 , AM4378 , AM4379

Trademarks
1Introduction
1. 1.1 Device and Development Support Tool Nomenclature
2. 1.2 Revision Identification
2All Errata Listed With Silicon Revision Number
3Usage Notes and Known Design Exceptions to Functional Specifications
1. 3.1 Usage Notes
  1. 3.1.1 LPDDR2/DDR3: JEDEC Compliance for Minimum Self-Refresh Command Interval
  2. 3.1.2 DDR3/DDR3L: JEDEC Specification Violation for DDR3 RESET Signal When Implementing RTC+DDR Mode
2. 3.2 Known Design Exceptions to Functional Specifications
  1. 3.2.1 Advisory List
  2. Advisory 1
  3. Advisory 2
  4. Advisory 3
  5. Advisory 4
  6. Advisory 5
  7. Advisory 6
  8. Advisory 7
  9. Advisory 8
  10. Advisory 9
  11. Advisory 10
  12. Advisory 11
  13. Advisory 12
  14. Advisory 13
  15. Advisory 14
  16. Advisory 15
  17. Advisory 16
  18. Advisory 17
  19. Advisory 19
  20. Advisory 20
  21. Advisory 21
  22. Advisory 22
  23. Advisory 24
  24. Advisory 25
  25. Advisory 26
  26. Advisory 27
  27. Advisory 28
  28. i2223
  29. i2224
  30. i912
  31. i2225
  32. i2226
4Revision History

i2224

DCAN: RAMINIT_DONE intermittently fails to latch completion

Revisions Affected

1.1, 1.2

Details

The DCAN_RAMINIT bits inside the CTRL_DCAN_RAMINIT register do not always capture the completion signal after the RAM has been initialized.

Workaround

The DCAN RAM initialization takes 69 DCAN ICLK cycles (The DCAN ICLK is driven by the L4 interconnect clock L4_PER_CLK). For a typical system with L4_PER_CLK=100 MHz, this corresponds to 690 ns. After the 0->1 transition of RAMINIT_START, the CAN registers should not be accessed for at least 69 DCAN ICLK cycles.