SPRZ408D June 2014 – June 2021 AM4372 , AM4376 , AM4377 , AM4378 , AM4379
Asynchronous Bridge Corruption
1.1, 1.2
If data is stalled inside an asynchronous bridge because of back pressure, it may be accepted multiple times and create pointer misalignment that corrupts the next transfers on that data path until the system is reset. There is no recovery procedure once the issue is hit because the path remains consistently broken. The async bridge can be found on the path between MPU to L3 interconnect (to EMIF) and Cortex M3 to L3 interconnect (to EMIF). This situation can happen only when the idle is initiated by a master request disconnection, which is trigged by software when executing WFI.
All the initiators connected through the asynchronous bridge must ensure that data path is properly drained before issuing WFI. This condition is met if one strongly ordered access is performed to the target right before executing the WFI.