SPRZ408D June 2014 – June 2021 AM4372 , AM4376 , AM4377 , AM4378 , AM4379
QSPI: QSPI register bitfield incorrectly masked when read
1.1, 1.2
Due to an integration error in the device, bits [25:24] (part of bitfield WLEN) of register QSPI_CMD_REG are masked and always read zero.
The bitfield functions correctly, as all bits in WLEN are writable. The errata only applies to reading the bitfield WLEN.