米6体育平台手机版

SPRZ412N December 2013 – May 2024 TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28378D , TMS320F28379D , TMS320F28379D-Q1

1
Abstract
1Usage Notes and Advisories Matrices
1. 1.1 Usage Notes Matrix
2. 1.2 Advisories Matrix
2Nomenclature, Package Symbolization, and Revision Identification
3Silicon Revision C Usage Notes and Advisories
1. 3.1 Silicon Revision C Usage Notes
2. 3.2 Silicon Revision C Advisories
  1. Advisory
  2. Advisory
  3. Advisory
  4. Advisory
  5. Advisory
  6. Advisory
  7. Advisory
  8. Advisory
  9. Advisory
  10. Advisory
  11. Advisory
  12. Advisory
  13. Advisory
  14. Advisory
  15. Advisory
  16. Advisory
  17. Advisory
  18. Advisory
  19. Advisory
  20. Advisory
  21. Advisory
  22. Advisory
  23. Advisory
  24. Advisory
  25. Advisory
  26. Advisory
  27. Advisory
  28. Advisory
  29. Advisory
  30. Advisory
  31. Advisory
  32. Advisory
  33. Advisory
  34. Advisory
  35. Advisory
  36. Advisory
  37. Advisory
  38. Advisory
4Silicon Revision B Usage Notes and Advisories
1. 4.1 Silicon Revision B Usage Notes
2. 4.2 Silicon Revision B Advisories
  1. Advisory
  2. Advisory
  3. Advisory
  4. Advisory
  5. Advisory
  6. Advisory
  7. Advisory
  8. Advisory
  9. Advisory
5Silicon Revision A Usage Notes and Advisories
1. 5.1 Silicon Revision A Usage Notes
2. 5.2 Silicon Revision A Advisories
  1. Advisory
  2. Advisory
  3. Advisory
  4. Advisory
  5. Advisory
  6. Advisory
  7. Advisory
  8. Advisory
  9. Advisory
  10. Advisory
  11. Advisory
6Silicon Revision 0 Usage Notes and Advisories
1. 6.1 Silicon Revision 0 Usage Notes
2. 6.2 Silicon Revision 0 Advisories
  1. Advisory
7Documentation Support
8Trademarks
9Revision History

Advisory

Flash: A Single-Bit ECC Error May Cause Endless Calls to Single-Bit-Error ISR

Revisions Affected

0, A, B, C

Details

When a single-bit ECC error is detected, the CPU executes the single-bit-error interrupt service routine (ISR). When the ISR returns, the same instruction that caused the first error is fetched again. If the ECC error threshold (ERR_THRESHOLD.THRESHOLD) is 0, then the same error is detected and another ISR is executed. This continues in an endless loop. This sequence of events only occurs if the error is caused by a program fetch operation, not a data read.

Workarounds

Set the error threshold bit-field (ERR_THRESHOLD.THRESHOLD) to a value greater than or equal to 1. Note that the default value of the threshold bit-field is 0.