Revisions Affected

B, C

Details

When the PLL is powered down (that is, SYPLLCTL1.PLLEN = 0) or bypassed (that is, SYSPLLCTL1.PLLCLKEN = 0), there is a necessary period of clock synchronization before the PLL bypass completes. During this time, if PLLSYSCLKDIV (or other clock divider) is set to a smaller value, the resulting system clock could be unexpectedly more than the rated device frequency.

Implementing the workaround below will allow the PLL bypass operation to complete before any other code is executed, ensuring expected device frequencies and proper system operation.

Workarounds

Add a software delay of 120 SYSCLK cycles using a NOP instruction while performing either a PLL power down or a PLL bypass operation.

Example:

SYSPLLCTL1.PLLCLKEN = 0;       // Bypassing the PLL
asm("  RPT #120 || NOP");      // Delay of 120 SYSCLK Cycles
SYSPLLCTL1.PLLEN = 0;          // Powering down the PLL
asm("  RPT #120 || NOP");      // Delay of 120 SYSCLK Cycles

The latest released C2000Ware, which has this workaround implemented, can be used as reference.