米6体育平台手机版

SPRZ423K October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076

1
Abstract
1Usage Notes and Advisories Matrices
1. 1.1 Usage Notes Matrix
2. 1.2 Advisories Matrix
2Nomenclature, Package Symbolization, and Revision Identification
3Silicon Revision C Usage Notes and Advisories
1. 3.1 Silicon Revision C Usage Notes
2. 3.2 Silicon Revision C Advisories
  1. Advisory
  2. Advisory
  3. Advisory
  4. Advisory
  5. Advisory
  6. Advisory
  7. Advisory
  8. Advisory
  9. Advisory
  10. Advisory
  11. Advisory
  12. Advisory
  13. Advisory
  14. Advisory
  15. Advisory
  16. Advisory
  17. Advisory
  18. Advisory
  19. Advisory
  20. Advisory
  21. Advisory
  22. Advisory
  23. Advisory
  24. Advisory
  25. Advisory
  26. Advisory
  27. Advisory
  28. Advisory
  29. Advisory
  30. Advisory
  31. Advisory
  32. Advisory
  33. Advisory
  34. Advisory
  35. Advisory
  36. Advisory
4Silicon Revision B Usage Notes and Advisories
1. 4.1 Silicon Revision B Usage Notes
2. 4.2 Silicon Revision B Advisories
  1. Advisory
  2. Advisory
  3. Advisory
  4. Advisory
  5. Advisory
  6. Advisory
  7. Advisory
  8. Advisory
  9. Advisory
5Documentation Support
6Trademarks
7Revision History

Advisory

ePIE: Spurious VCU Interrupt (ePIE 12.6) Can Occur When First Enabled

Revisions Affected

Details

The VCU-II can power up in a state which incorrectly sets the VCU VSTATUS[DIVE] error bit and, subsequently PIEIFR12[INTx6], when the CPU is released from reset. When the VCU interrupt enable PIEIER12[INTx6] is enabled for the first time by the application, a spurious interrupt can occur due to the erroneous pending interrupt.

Workarounds

Before enabling VCU interrupt 12.6, execute the following instructions to avoid the spurious interrupt.


// Clear VCU divide by zero status
asm(" VCLRDIVE");
// Clear PIE interrupt for VCU
PieCtrlRegs.PIEIFR12.bit.INTx6 = 0;

Beginning with revision C silicon, the Boot ROM will perform the above workaround before branching to the application.