米6体育平台手机版

SPRZ423K October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076

1
Abstract
1Usage Notes and Advisories Matrices
1. 1.1 Usage Notes Matrix
2. 1.2 Advisories Matrix
2Nomenclature, Package Symbolization, and Revision Identification
3Silicon Revision C Usage Notes and Advisories
1. 3.1 Silicon Revision C Usage Notes
2. 3.2 Silicon Revision C Advisories
  1. Advisory
  2. Advisory
  3. Advisory
  4. Advisory
  5. Advisory
  6. Advisory
  7. Advisory
  8. Advisory
  9. Advisory
  10. Advisory
  11. Advisory
  12. Advisory
  13. Advisory
  14. Advisory
  15. Advisory
  16. Advisory
  17. Advisory
  18. Advisory
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  20. Advisory
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  22. Advisory
  23. Advisory
  24. Advisory
  25. Advisory
  26. Advisory
  27. Advisory
  28. Advisory
  29. Advisory
  30. Advisory
  31. Advisory
  32. Advisory
  33. Advisory
  34. Advisory
  35. Advisory
  36. Advisory
4Silicon Revision B Usage Notes and Advisories
1. 4.1 Silicon Revision B Usage Notes
2. 4.2 Silicon Revision B Advisories
  1. Advisory
  2. Advisory
  3. Advisory
  4. Advisory
  5. Advisory
  6. Advisory
  7. Advisory
  8. Advisory
  9. Advisory
5Documentation Support
6Trademarks
7Revision History

Advisory

During DCAN FIFO Mode, Received Messages May be Placed Out of Order in the FIFO Buffer

Revisions Affected

B, C

Details

In DCAN FIFO mode, received messages with the same arbitration and mask IDs are supposed to be placed in the FIFO in the order in which they are received. The CPU then retrieves the received messages from the FIFO via the IF1/IF2 interface registers. Some messages may be placed in the FIFO out of the order in which they were received. If the order of the messages is critical to the application for processing, then this behavior will prevent the proper use of the DCAN FIFO mode.

Workarounds

None