SPRZ423K October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
ADC: 12-Bit Input Capacitance When Switching Channel Groups
B
The ADC input model should be used to select the sample-and-hold (S+H) duration for each ADC input. For the revisions affected, if the currently converting channel is an even-numbered channel and the previously converted channel was an odd-numbered channel (or vice versa), then the 12-bit input model will not accurately predict ADC input performance. Under these conditions, an additional capacitance should be added to the model. This capacitance has a value of 11.5 pF and should be placed between the S+H switch and Ron as shown in Figure 4-1.
For the revisions affected, when subsequent conversions switch between channel groups, the S+H duration should be chosen to account for the additional capacitance.