CRITICALITY

High

DESCRIPTION

Following a warm Power-on-Reset (PORz) event, in which the supplies to the SoC remain ON throughout the assertion of PORz, the boot process may hang if the SoC is within a narrow temperature range.

The sensitive temperature range can be different on each device, is typically ~5^oC wide, and typically occurs below 25^oC.

The boot issue occurs only when the PORz signal is asserted to the SoC without turning-off the supplies to the SoC. No issue is observed in normal cold-boot operation in which the SoC boots up from a full power-off condition.

This erratum does not occur in typical use case scenarios. The boot hang may occur only if the PORz event is generated as a consequence of some other issue (e.g., runtime reset from an external MCU, or an SoC watchdog timer expiration resulting in PORz assertion) while the SoC temperature is within a narrow range.

The issue results from improper power sequencing to an internal SRAM that is accessed during execution of the early stages of the boot process. During assertion of PORz, the SoC's on-chip LDO regulator supplying the SRAM tri-states its output, thus allowing internal supplies to the SRAM to drift down uncontrolled. This can result in improper sequencing as the LDO reapplies power to the SRAM upon de-assertion of PORz before internal supplies to the SRAM have fully ramped down. This situation can result in incorrect accesses to the SRAM during boot, causing the boot process to halt.

WORKAROUND

A board level workaround requires adding a 220 Ohm (+/- 5%) resistor onto the SRAM LDO supply (Cap_vddram_mpu2, ball K19). This resistor provides a controlled discharge path for the charge contained within the external 1uF LDO capacitor during the reset operation. The workaround effectiveness assumes that the active duration of the PORz signal is a typical 3.4ms or greater.

In systems with an MCU present, a second workaround technique can be utilized. The MCU performs a handshake with the device following a warm PORz to ensure that the device is responsive after the reset. On the occasion a hang occurs, the MCU should assert PORZ low for 200 ms. This eliminates the need for an external 220 Ohm resistor.

REVISIONS IMPACTED

DRA72x SR 1.0

TDA2Ex (23mm): 1.0

AM571x: 1.0

DRA72x: 1.0