CRITICALITY

Medium

DESCRIPTION

When warm reset is asserted, EMIF will preserve the contents of the DDR by entering self-refresh. During warm reset the DDR clock source is set to a slower PLL bypass than during normal operation. This causes the following JEDEC spec violations and could result in a DDR access hang after warm reset:

• DDR clock frequency to the DDR memory is lower than the JEDEC min. clock frequency specified as tCK(avg) min parameter in the JEDEC JESD79-3F DDR3 standard
• Upon warm reset de-assertion, DDR is taken out of self-refresh and DDR clock frequency is changed from PLL bypass to normal operating frequency. This violates the JEDEC JESD79-3F DDR3 standard that requires input clock to be stable during normal operation

WORKAROUND

There are 2 possible work-arounds:

1. Use workaround as outlined in Errata i862 to convert warm reset to PORz. Warm reset will function the same as cold reset with this approach .
2. Use external circuitry to apply reset on DDR RESET# pin when warm reset is asserted. DDR contents will be erased upon warm reset with this approach.

REVISIONS IMPACTED

DRA72x SR 2.0, 1.0
DRA71x SR 2.1, 2.0

DRA79x: 2.1, 2.0

TDA2Ex (23mm): 2.0, 1.0

TDA2Ex (17mm): 2.1, 2.0

AM571x: 2.1, 2.0, 1.0

AM570x: 2.1, 2.0

DRA72x: 2.0, 1.0

DRA71x: 2.1, 2.0