CRITICALITY

Low

DESCRIPTION

Consider the following scenario:

1. Initialize SATA.
2. Enable TX/RX PHYs, start controller DMA engine, spin up the device (SATA_PxCMD[1] SUD = 0x1).
3. Enable aggressive transitions to partial or slumber: SATA_PxCMD[26] ALPE = 0x1 and SATA_PxCMD[27] = 0x0/0x1
4. Perform DMA/PIO transfers.
5. Wait until all commands are finished. Interface (only physical lines) should go to low power mode.
6. Check that transition to partial is complete.
7. Stop all DMA machines, set SATA_PxCMD[1] SUD bit to 0, power down the PHYs.
8. Unlock SATA DPLL (DPLLCTRL_SATA.PLL_GO[0] PLL_GO = 0x0)
9. Relock SATA DPLL (DPLLCTRL_SATA.PLL_GO[0] PLL_GO = 0x1), go out to low power mode.
10. Go to Step 2.

After the first loop, when re-executing Step 2 and spinning up the device, communication is blocked between the host and the device, and the SATA is locked up.

A simpler scenario can be used to reproduce the issue. In this case, no SATA commands are issued by the host.

1. Initialize the SATA.
2. Enable PHYs, start RX DMA engine, initiate staggered spin-up, and start TX DMA engine.
3. Read SATA status register SATA_PxTFD.
4. Stop all DMA engine, set SATA_PxCMD[1] SUD bit to 0, power down the PHYs.
5. Unlock and relock SATA DPLL (DPLLCTRL_SATA.PLL_GO[0] PLL_GO = 0x0 then DPLLCTRL_SATA.PLL_GO[0] PLL_GO = 0x1).
6. Go to Step 2.

These issues are usually encountered immediately after the first loop, although this is not always the case.

WORKAROUND

To prevent the SATA Lockup the SATA DPLL Unlock sequence must be performed as follows:

1. Unlock SATA DPLL (DPLLCTRL_SATA.PLL_GO[0] PLL_GO = 0x0)
2. Toggle SATA_PLL_SOFT_RESET bit of CTRL_CORE_SMA_SW_0 register from 0->1
3. Toggle SATA_PLL_SOFT_RESET bit of CTRL_CORE_SMA_SW_0 register from 1->0

REVISIONS IMPACTED

DRA72x SR 2.0, 1.0

TDA2Ex (23mm): 2.0, 1.0

AM571x: 2.1, 2.0, 1.0

DRA72x: 2.0, 1.0