CRITICALITY

Medium

DESCRIPTION

The following pins are not controllable via Boundary Scan (BSDL) if the resetn signal was deasserted (high) anytime during or between power-up and the Boundary Scan (BSDL) testing: gpmc_a12, gpmc_a13, gpmc_a18, gpmc_a23, gpmc_a7, gpmc_wen, mmc3_clk, uart1_ctsn, ddr1_csn0, ddr1_wen, mmc1_clk.

If resetn remains asserted (low) during and between power-up and Boundary Scan (BSDL) testing, then the listed pins are controllable.

All other signals are controllable with resetn asserted (low) or deasserted (high).

WORKAROUND

In order to control the listed pins with Boundary Scan (BSDL), the resetn signal should remain asserted (low) during and between Device power-up and Boundary Scan (BSDL) operation.

As an example, this can be accomplished by providing a test-point for the resetn signal on the PCB. During and between Device power-up and Boundary Scan (BSDL) operation, a bed-of-nails test harness can force a logic-0 onto that test-point.

If the resetn signal cannot be asserted low during and between Device power-up and Boundary Scan (BSDL) testing, then functional test cases can be used to confirm connectivity on the PCB during manufacturing.

REVISIONS IMPACTED

DRA72x SR 2.0
DRA71x SR 2.1, 2.0

DRA79x: 2.0

TDA2Ex (23mm): 2.0

TDA2Ex (17mm): 2.1, 2.0

AM571x: 2.1, 2.0

AM570x: 2.1, 2.0

DRA72x: 2.0

DRA71x: 2.1, 2.0