米6体育平台手机版

SPRZ426F November 2014 – September 2024 DRA710 , DRA712 , DRA714 , DRA716 , DRA718 , DRA722 , DRA724 , DRA725 , DRA726

1
1Introduction
1. Related Documentation
2. Trademarks
3. Modules Impacted
2Silicon Advisories
1. Revisions SR 2.1, 2.0, 1.0 - Advisories List
2. i202
3. i378
4. i631
5. i694
6. i698
7. i699
8. i709
9. i727
10. i729
11. i734
12. i767
13. i782
14. i783
15. i802
16. i803
17. i807
18. i808
19. i809
20. i810
21. i813
22. i814
23. i815
24. i818
25. i819
26. i820
27. i824
28. i826
29. i829
30. i834
31. i849
32. i856
33. i862
34. i863
35. i867
36. i868
37. i869
38. i870
39. i871
40. i872
41. i874
42. i875
43. i878
44. i879
45. i880
46. i881
47. i882
48. i883
49. i887
50. i889
51. i890
52. i893
53. i895
54. i896
55. i897
56. i898
57. i899
58. i900
59. i903
60. i904
61. i906
62. i913
63. i916
64. i927
65. i928
66. i929
67. i930
68. i932
69. i933
70. i940
71. i2446
3Silicon Limitations
1. Revisions SR 2.1, 2.0, 1.0 - Limitations List
2. i596
3. i641
4. i833
5. i838
6. i844
7. i845
8. i848
9. i876
10. i877
11. i892
12. i909
13. i917
4Silicon Cautions
1. Revisions SR 2.1, 2.0, 1.0 - Cautions List
2. i781
3. 4.1 95
4. i827
5. i832
6. i836
7. i839
8. i864
9. i885
10. i886
11. i912
12. i918
13. i920
14. i926
15. i931
16. i934
17. 4.2 109
5Revision History

i378

sDMA Channel Is Not Disabled after a Transaction Error

CRITICALITY

Medium

DESCRIPTION

In case of destination synchronized transfer on the write port (or source sync with SDMA.DMA4_CCRi[25] BUFFERING_DISABLE = 1), if a transaction error is reported at the last element of the transaction, the channel is not automatically disabled by DMA.

WORKAROUND

Whenever a transaction error is detected on a transaction on the write side of the channel i, software must disable the channel(i) by setting the DMA4_CCRi[7] ENABLE bit to 0.

REVISIONS IMPACTED

DRA72x SR 2.0, 1.0
DRA71x SR 2.1, 2.0

DRA79x: 2.1, 2.0

TDA2Ex (23mm): 2.0, 1.0

TDA2Ex (17mm): 2.1, 2.0

AM571x: 2.1, 2.0, 1.0

AM570x: 2.1, 2.0

DRA72x: 2.0, 1.0

DRA71x: 2.1, 2.0