CRITICALITY

Medium

DESCRIPTION

When running the CSI2 interface at greater than 600MHz (1.2Gbps per lane), setup/hold times are not compliant with limits required by the MIPI CSI2 DPHY specification. Systems using the CSI2 interface at less than or equal to 600MHz are not affected.

WORKAROUND

Since the CSI2 interface includes up to 4 data lanes (plus 1 clock lane), data can be distributed across multiple lanes in order to keep the clock rate lower. Otherwise, the output delay timings of the external CSI2 transmitter device should be analyzed in comparison with the setup/hold timing requirements of the CSI2 receiver to confirm timing compatibility before attempting to run the interface at frequencies above 600MHz. Consult your local TI representative for more information on CSI2 receiver setup/hold timings at frequencies above 600MHz.

REVISIONS IMPACTED

DRA72x SR 2.0, 1.0
DRA71x SR 2.1, 2.0

DRA79x: 2.1, 2.0

TDA2Ex (23mm): 2.0, 1.0

TDA2Ex (17mm): 2.1, 2.0

AM571x: 2.1, 2.0, 1.0

AM570x: 2.1, 2.0

DRA72x: 2.0, 1.0

DRA71x: 2.1, 2.0