CRITICALITY

Medium

DESCRIPTION

In rare circumstances the DPLL_VIDEO1 and DPLL_VIDEO2 PLLs may not lock on the first attempt during SoC initialization. When this occurs a subsequent attempt to relock the PLL will result in the PLL successfully locking.

WORKAROUND

In order to successfully lock the PLL, the following software sequence is recommended:

1. Boot SoC.
2. Configure DPLL_VIDEO1.
3. Set PLL_GO[0] PLL_GO bit to trigger Lock sequence.
4. Poll for Status bits in Locked, Non-error state OR Wait for Timeout (1000 REFCLK cycles):
   • PLL_STATUS[6] PLL_BYPASS = 0
   • PLL_STATUS[5] PLL_HIGHJITTER = 0
   • PLL_STATUS[3] PLL_LOSSREF = 0
   • PLL_STATUS[2] PLL_RECAL = 0
   • PLL_STATUS[1] PLL_LOCK = 1
   • PLL_STATUS[0] PLLCTRL_RESET_DONE = 1
5. If Fail to Lock/Error -> Set PLL_GO[0] PLL_GO bit again; Repeat up to 20 times.

REVISIONS IMPACTED

DRA72x SR 2.0, 1.0
DRA71x SR 2.1, 2.0

DRA79x: 2.1, 2.0

TDA2Ex (23mm): 2.0, 1.0

TDA2Ex (17mm): 2.1, 2.0

AM571x: 2.1, 2.0, 1.0

AM570x: 2.1, 2.0

DRA72x: 2.0, 1.0

DRA71x: 2.1, 2.0