CRITICALITY

High

DESCRIPTION

The MPU has two primary paths to DDR and system address space via the MPU Memory Adapter (MPU_MA).

The Low Latency path is the predominant path for DDR accesses and provides direct/low latency/interleaved access to the two EMIFs.

The L3 Interconnect path (via MPU_AXI2OCP bridge) is most typically used for access to non-DDR address space, but is also used for access to DMM and EMIF control registers and to Tiled regions of DDR address space.

Issue is seen to come when there is a heavy memory access through the MPU L3 path, if the MPU is concurrently issuing write transactions via the Low Latency path to DDR and via the L3 Interconnect to the DMM/EMIF/Tiler address space then the transactions can hang and the MPU and DMM/DDR become unresponsive. A device reset is required in order to recover from this condition.

WORKAROUND

In order to completely avoid the issue, the MPU can avoid concurrent accesses to the DMM/EMIF/DDR address space via the Low Latency path and the L3 Interconnect path. In order to accomplish this, the MPU should avoid use of the L3 Interconnect path via the MPU by using DSP, IPU, or DMA to proxy accesses to the EMIF/DMM registers or Tiler DDR address space.

In order to greatly reduce the probability of the issue occurring, the MPU_MA register at 0x482AF400 bits 2 and 1 can be set, that is, 0x482AF400 |= 0x6. With this setting of MPU_MA register, the 3 different heavily loaded application scenario which earlier reproduced the issue was seen working fine for long duration testing.

Note: The MPU_MA register is a valid register address location even though it is located outside the MPU memory space as specified in the device TRM.

REVISIONS IMPACTED

DRA72x SR 2.0, 1.0
DRA71x SR 2.1, 2.0

DRA79x: 2.1, 2.0

TDA2Ex (23mm): 2.0, 1.0

TDA2Ex (17mm): 2.1, 2.0

AM571x: 2.1, 2.0, 1.0

AM570x: 2.1, 2.0

DRA72x: 2.0, 1.0

DRA71x: 2.1, 2.0