CRITICALITY

Medium

DESCRIPTION

Because of a glitchy structure inside the UART module, accessing the MDR1 register may create a dummy underrun condition and freeze the UART in IrDa transmission. In UART mode, this may corrupt the transferred data(received or transmitted).

WORKAROUND

To ensure this problem does not occur, the following software initialization sequence must be used each time MDR1 must be changed:

1. If needed, setup the UART by writing the required registers, except MDR1
2. Set appropriately the bit field
3. Wait for 5 L4 clock cycles + 5 UART functional clock cycles
4. Clear TX and RX FIFO in FCR register to reset its counter logic
5. Read RESUME register to resume the halted operation

REVISIONS IMPACTED

DRA72x SR 2.0, 1.0
DRA71x SR 2.1, 2.0

DRA79x: 2.1, 2.0

TDA2Ex (23mm): 2.0, 1.0

TDA2Ex (17mm): 2.1, 2.0

AM571x: 2.1, 2.0, 1.0

AM570x: 2.1, 2.0

DRA72x: 2.0, 1.0

DRA71x: 2.1, 2.0