SPRZ426F November 2014 – September 2024 DRA710 , DRA712 , DRA714 , DRA716 , DRA718 , DRA722 , DRA724 , DRA725 , DRA726
DLL SW Reset Bit Does Not Reset to 0 after Execution
Medium
When autoidle is enabled (MMCHS_SYSCONFIG[0] AUTOIDLE = 0x1), clock gets cut off and the reset completion signal would not be recorded by the processor. Hence, though the reset executed and finished, the MMCHS_DLL[31] DLL_SOFT_RESET flag will remain asserted indefinitely and another soft reset will be ignored.
Disable autoidle (MMCHS_SYSCONFIG[0] AUTOIDLE = 0x0), before DLL reset and reenable autoidle after the reset.
Set MMCHS_SYSCONFIG[0] AUTOIDLE = 0 before reset.
Set MMCHS_SYSCONFIG[0] AUTOIDLE = 1 after the reset.
DRA72x SR 2.0, 1.0
DRA71x SR 2.1, 2.0
DRA79x: 2.1, 2.0
TDA2Ex (23mm): 2.0, 1.0
TDA2Ex (17mm): 2.1, 2.0
AM571x: 2.1, 2.0, 1.0
AM570x: 2.1, 2.0
DRA72x: 2.0, 1.0
DRA71x: 2.1, 2.0