米6体育平台手机版

SPRZ436H October 2015 – July 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL

1
1Introduction
1. Related Documentation
2. Trademarks
3. Modules Impacted
2Silicon Advisories
1. Revisions SR 2.1, 2.0, 1.0 - Advisories List
2. i202
3. i378
4. i631
5. i694
6. i698
7. i699
8. i709
9. i727
10. i729
11. i734
12. i767
13. i782
14. i783
15. i802
16. i803
17. i807
18. i808
19. i809
20. i810
21. i813
22. i814
23. i815
24. i818
25. i819
26. i820
27. i824
28. i826
29. i829
30. i834
31. i849
32. i856
33. i862
34. i863
35. i867
36. i868
37. i869
38. i870
39. i871
40. i872
41. i874
42. i875
43. i878
44. i879
45. i880
46. i882
47. i883
48. i887
49. i889
50. i890
51. i893
52. i895
53. i896
54. i897
55. i898
56. i899
57. i900
58. i903
59. i904
60. i906
61. i907
62. i913
63. i916
64. i927
65. i928
66. i929
67. i930
68. i932
69. i933
70. i936
71. i940
72. i2446
3Silicon Limitations
1. Revisions SR 2.1, 2.0, 1.0 - Limitations List
2. i596
3. i641
4. i833
5. i838
6. i845
7. i848
8. i876
9. i877
10. i892
11. i909
12. i922
13. i925
4Silicon Cautions
1. Revisions SR 2.1, 2.0, 1.0 - Cautions List
2. i827
3. i832
4. i836
5. i839
6. i864
7. i885
8. i886
9. i912
10. i918
11. i920
12. i921
13. i926
14. i931
15. i934
16. i935
5Revision History

i378

sDMA Channel Is Not Disabled after a Transaction Error

CRITICALITY

Medium

DESCRIPTION

In case of destination synchronized transfer on the write port (or source sync with SDMA.DMA4_CCRi[25] BUFFERING_DISABLE = 1), if a transaction error is reported at the last element of the transaction, the channel is not automatically disabled by DMA.

WORKAROUND

Whenever a transaction error is detected on a transaction on the write side of the channel i, software must disable the channel(i) by setting the DMA4_CCRi[7] ENABLE bit to 0.

REVISIONS IMPACTED

AM571x SR 2.1, 2.0, 1.0
AM570x SR 2.1, 2.0

DRA79x: 2.1, 2.0

TDA2Ex (23mm): 2.0, 1.0

TDA2Ex (17mm): 2.1, 2.0

AM571x: 2.1, 2.0, 1.0

AM570x: 2.1, 2.0

DRA72x: 2.0, 1.0

DRA71x: 2.1, 2.0