CRITICALITY

Medium

DESCRIPTION

Glitches up to multiple nano-seconds in length can occur on a Device IO when changing the IO setting via either of the below methods:

1. Changing the value of the MUXMODE, DELAYMODE or MODESELECT fields of the corresponding CTRL_CORE_PAD_* register.
2. Changing the value of the CFG_*_IN, CFG_*_OEN, and CFG_*_OUT registers in the IODELAYCONFIG Module.

WORKAROUND

To workaround this issue, the Device LVCMOS IOs should be placed into Isolation mode when changing the IO settings as described above. Refer to the Device TRM section "Isolation Requirements" for more details.

REVISIONS IMPACTED

AM571x SR 2.1, 2.0, 1.0
AM570x SR 2.1, 2.0

DRA79x: 2.1, 2.0

TDA2Ex (23mm): 2.0, 1.0

TDA2Ex (17mm): 2.1, 2.0

AM571x: 2.1, 2.0, 1.0

AM570x: 2.1, 2.0

DRA72x: 2.0, 1.0

DRA71x: 2.1, 2.0