Revision Affected

A

Details

If a voltage greater than maximum V_IH (V_DDIO + 0.3 V) is applied to the GPIO pins listed below, an internal parasitic path from the pin to V_SS may be turned on. This parasitic current can impact the functional operation of the pin. This is more likely to occur at high temperature. The parasitic path will be removed when the IO is driven below V_IL. The path will not reactivate until another overvoltage event occurs.

• GPIO16
• GPIO17
• GPIO24
• GPIO25
• GPIO26
• GPIO27
• GPIO35 (TDI)
• GPIO37 (TDO)
• GPIO40
• GPIO41
• GPIO42
• GPIO43

Pins configured for output-only mode (with no other drivers on the pin) will not see an overvoltage condition at the pin and are not affected by this advisory.

Pins configured in input or bidirectional mode can see an overvoltage condition in three primary ways:

1. The input is driven by a low-impedance driver that can generate a large overshoot at the input due to impedance mismatch without compensating termination.
2. The input sees large transients from external noise sources that rise above V_DDIO + 0.3 V at the pin.
3. The input is driven by a device powered by a different voltage regulator. When receiving voltages from another voltage domain, the system design should always keep voltages below maximum V_IH. However, due to the increased possibility of the voltage being temporarily greater than V_DDIO + 0.3 V due to a noise event or if there is improper supply sequencing, then this advisory will apply.

Workaround

If any of the above conditions apply for an input or bidirectional pin, insert a series resistor between the signal and the input pin. The series resistor should be placed close to the input pin.

If the overvoltage is due to overshoot (situations #1 or #2 above), a series resistor of 100 Ω or greater should be used.

If the overvoltage might be sustained (situation #3 above), a series resistor of 220 Ω or greater should be used.