SPRZ439H January 2017 – February 2024 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
ADC: Degraded ADC Performance With ADCCLK Fractional Divider
0, A, B
Using fractional SYSCLK-to-ADCCLK dividers (controlled by the ADCCTL2.PRESCALE field) has been shown to cause degradation in ADC performance on this device. See Table 3-4.
REDUCED PERFORMANCE | |||
---|---|---|---|
BIT | FIELD | VALUE | DESCRIPTION |
3–0 | PRESCALE | 0001 | ADCCLK = SYSCLK/1.5 |
0003 | ADCCLK = SYSCLK/2.5 | ||
... | |||
NORMAL PERFORMANCE | |||
BIT | FIELD | VALUE | DESCRIPTION |
3–0 | PRESCALE | 0000 | ADCCLK = SYSCLK/1.0 |
0002 | ADCCLK = SYSCLK/2.0 | ||
... |
Use even PRESCALE clock divider values. Even PRESCALE values result in integer clock dividers which do not impact the ADC performance.