CRITICALITY

Low

DESCRIPTION

A bug in the SATA core is integrated into the SATA controller.

The host fails to proceed when receiving a D2H PIO setup FIS with bus busy (BSY) and data request (DRQ) bits cleared.

When the three following events occur simultaneously, the host controller fails to proceed and locks up:

• Host controller receives a PIO setup FIS (D=0/write):
  • SATA_PxIS[1] PSS = 0x1
• SATA_PxTFD[7] STS_BSY bit is cleared
• SATA_PxTFD[3] STS_DRQ bit is cleared

The bug is due to a state-machine in the SATA core that is not well implemented for this scenario.

A reset is required to continue communication between the host and the device.

From a user point of view, the impact can be some latency that is seen while proceeding.

WORKAROUND

Implement a software time-out for locks and then issue one of the followoing two resets, first the least intrusive and/or more intrusive if it does not solve the lock.

Least intrusive, software reset:

• To issue a software reset, the user must prepare two H2D register FISs into the emptied command list of the port:
  • The first FIS must have bits SRST = 0b1 and C = 0b0. The first FIS corresponding command header bits C and R are set as follows: C = 0b1 and R = 0b1.
  • The second FIS has bits SRST = 0b0 and C = 0b0. The second FIS corresponding command header bits C and R are set as follows: C = 0b0 and R = 0b0.

More intrusive, Port reset (or COMRESET):

• SATA_PxSCTL[3:0] DET = 0x1

REVISIONS IMPACTED

SR 1.0

AM574x: 1.0

DRA75xP, DRA74xP, DRA77xP, DRA76xP: 1.0

TDA2Px: 1.0

AM576x: 1.0