SPRZ450B February 2018 – September 2024 DRA74P , DRA75P , DRA76P , DRA77P
DLL SW Reset Bit Does Not Reset to 0 after Execution
Medium
When autoidle is enabled (MMCHS_SYSCONFIG[0]AUTOIDLE=0x1), clock gets cut off and the reset completion signal would not be recorded by the processor. Hence, though the reset executed and finished, the MMCHS_DLL[31]DLL_SOFT_RESET flag will remain asserted indefinitely and another soft reset will be ignored.
Disable autoidle (MMCHS_SYSCONFIG[0]AUTOIDLE=0x0), before DLL reset and re-enable autoidle after the reset.
Set MMCHS_SYSCONFIG[0]AUTOIDLE = 0 before reset
Set MMCHS_SYSCONFIG[0]AUTOIDLE = 1 after the reset
SR 1.0
AM574x: 1.0
DRA75xP, DRA74xP, DRA77xP, DRA76xP: 1.0
TDA2Px: 1.0
AM576x: 1.0