SPRZ450B February 2018 – September 2024 DRA74P , DRA75P , DRA76P , DRA77P
SATA Command Does Not Complete and Software Must Issue a Port Reset Under Certain Conditions
Medium
When a Device-to-Host register FIS is received from the device and the FIS length exceeds eight DWORDs, the command may not complete due to an internal receive FIFO overflow condition. As a consequence, the host controller is locked and a latency is seen.
The length of the FIS is specified by the specification and having more is a specification violation/error case.
The issue is how a host controller is implemented.
A port reset (COMRESET) must be done to reestablish the communication between the host and the device.
SR 1.0
AM574x: 1.0
DRA75xP, DRA74xP, DRA77xP, DRA76xP: 1.0
TDA2Px: 1.0
AM576x: 1.0