Details:

In LPDDR4 mode, if software sends a Mode Register Write (MRW) command using the MRCTRL0 and MRCTRL1 registers while read/write transactions are being executed, a read/write command can be followed by a MRW command resulting in a read to MRW, or a write to MRW command timing violation.

Workaround(s):

Perform software initiated MRW commands after entering self-refresh mode by performing the following sequence:

1. Disable PHY master interface

• Set DFIPHYMSTR.dfi_phymstr_en to 0 (note that this is documented as static, but implemented as dynamic register)

2. Disable the following automatic self-refresh entry (if using)

• Set PWRCTL.selfref_en to 0

3. Ensure that DDR is not in self-refresh or SR-Powerdown.

• Wait for STAT.operating_mode to be not equal to 3'b011 (Self-Refresh/SR-Powerdown mode)

4. Enter self-refresh 1 state

• Set PWRCTL.stay_in_selfref to 1
• Set PWRCTL.selfref_sw to 1
• Wait for STAT.selfref_type to be not equal to 2'b01 (Self-Refresh caused by PHY master request)
• If STAT.selfref_state is 2'b10 (SR-Powerdown) or 2'b11(Self-Refresh 2), set PWRCTL.stay_in_selfref to 0 and PWRCTL.selfref_sw to 0, then go back to step 2
• Wait for STAT.selfref_state to become 2'b01 (Self-Refresh 1)

5. Send MRW commands using MRCTRL0 and MRCTRL1 registers

6. Enter SR-Powerdown mode.

• Set PWRCTL.stay_in_selfref to 0
• Wait for STAT.selfref_state to become 2'b10 (SR-Powerdown)

7. Exit self-refresh mode.

• Set PWRCTL.selfref_sw to 0
• Wait for STAT.selfref_state to become 2'b00 (Not Self-Refresh)

8. Enable PHY master interface

• Set DFIPHYMSTR.dfi_phymstr_en to 1