Table 1-1 lists all usage notes and the applicable silicon revision(s). Table 1-2 lists all advisories, modules affected, and the applicable silicon revision(s).
ID | DESCRIPTION | SILICON REVISIONS AFFECTED | ||
---|---|---|---|---|
AM65x | ||||
2.1 | 2.0 | 1.0 | ||
i2033 | Section 3.1.1 — Fail-Safe IO's: Latch-up Risk on Fail-Safe IOs | Yes | Yes | Yes |
i2082 | Section 3.1.2 — ADC: High Input Leakage Current May Impact ADC Accuracy | Yes | ||
i2007 | Section 3.1.3 — INTRTR: Spurious Interrupts Generated when Programming Certain Interrupt Routers | Yes | Yes | Yes |
i2351 | Section 3.1.4 — OSPI: Controller does not support Continuous Read mode with NAND Flash | Yes | Yes | Yes |
MODULE | DESCRIPTION | SILICON REVISIONS AFFECTED | ||
---|---|---|---|---|
AM65x | ||||
2.1 | 2.0 | 1.0 | ||
ADC | i2151 — ADC: Debounce time control register | Yes | Yes | |
Boot, USB3SS | i2019 — Boot, USB3SS: Boot ROM Does Not Support USB Host MSC (Mass Storage Class) Boot Mode | Yes | ||
i2020 — Boot, USB3SS: Boot ROM Does Not Support USB Device Firmware Upgrade (DFU) Boot Mode | Yes | |||
Boot, UART |
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for example, AM6546). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
Support tool development evolutionary flow:
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
For additional information how to read the complete device name for any AM654x and AM652x devices, see the specific-device Datasheet (SPRSP08, SPRSP31).
Figure 2-1 shows an example of package symbolization.
Table 2-1 lists the device revision codes.
DEVICE REVISION CODE | SILICON REVISION | COMMENTS |
---|---|---|
BLANK | 1.0 | Available as null. |
A | 2.0 | |
B | 2.1 |
This section lists the usage notes and advisories for this silicon revision.
AM65x silicon revision 1.0, 2.0, and 2.1 incorporate fail-safe I/O’s on several pins (I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA, and NMIn). The fail safe I/O’s tolerate voltage applied on the pins before their respective I/O supply voltage is ramped up. There is a potential latch up risk based on design reviews of the fail-safe I/O pins when driven high during functional mode. This latch-up risk is not yet confirmed through silicon characterization. To avoid the risk of a latch-up condition, the following steps should be implemented, depending on the mux mode used on the fail safe I/O. If the fail safe I/O is used in an I2C mux mode, then an external pull-up resistor (> 1 kOhm) is required on the signal. If the fail safe I/O is used in any other mux mode, then an external series resistor (> 1 kOhm) should be placed on this signal (close to the SoC).
On AM65x silicon revision 1.0, ADC input leakage current may be higher than expected at worst case Process/Voltage/Temperature (PVT) conditions, where process variation and operating temperature are the major contributors. Leakage current is larger for strong process devices operating at elevated temperatures.
There is also a dependency on the potential applied to an ADC input. Leakage current flows out of the ADC when applying a potential equal to VSS, flows into the ADC when applying a potential equal to VDDA_ADC_MCU, and the direction change occurs at approximately 42% of VDDA_ADC_MCU. Magnitude of leakage current has a non-linear function to the applied potential, where it increases exponentially as the applied potential approached VSS or VDDA_ADC_MCU.
Significant error can be introduced in ADC measurements when high impedance sources are connected to inputs with high leakage. This occurs because the input leakage current introduces a voltage drop across the source impedance. For example, the ADC would measure a potential of 1.45 V when measuring a 1.5 V source with 1 kΩ output impedance that is connected to an ADC input with 50 µA of leakage flowing into the ADC input. The error of this measurement would be 50 mV, which is 3.3% lower than the expected value. Reducing the source impedance from 1 kΩ to 100 Ω in this example would reduce the measurement error to 0.33%.
There are design techniques that can be used to minimize the impact of input leakage.
Reduce impedance of sources connected to ADC inputs. For example, it may be necessary to buffer outputs of a high impedance sources with voltage-follower operational amplifier circuits.
Design static DC sources to apply a nominal potential of approximately 42% of VDDA_ADC_MCU. For example, this approach can be used to minimize leakage when monitoring a DC power source via a resistor voltage divider.