SPRZ452I july 2018 – may 2023 AM6526 , AM6528 , AM6546 , AM6548
DCC: Incorrect Counter Values in DCC Operation
AM65x SR 1.0
Due to a potential race condition, if the DCCCNT0, DCCCNT1, DCCCNTSEED0, or DCCCNTSEED1 registers are modified while a DCC module is in operation or immediately before a DCC module is put in to operation, the counter may not expire correctly as per the programmed counter value (expiring either late or early). This could result in an incorrect error signal value, indicating either a false pass or fail.
All DCC configuration fields, especially counter seeds and values, should be programmed while the DCC module is disabled. A user may also read back the last written counter value in the DCCCNT0 and DCCCNT1 registers before enabling the DCC module to ensure that counter values have had ample time to settle before the DCC module is enabled.