CRITICALITY

High

DESCRIPTION

Processor operation requires strict power requirements on the system (Processor + Power Management IC + Power Distribution Network).

The Processor requires carefully controlled system margin validation and verification.

In GHz systems, instability could result from marginal board design, component selection, power supply transients, susceptibility to noise, and so forth.

Developers must optimize PDN board designs to ensure stable operation at all OPP's across all conditions and over the lifetime of the system. The necessary steps to follow to ensure robust operation are listed in the following Guidelines section.

GUIDELINES

• Software guidelines:
  1. It is mandatory to use SmartReflex technology for the AVS power rails (MPU, CORE, DSPEVE, GPU, etc.). Refer to the Data Manual for AVS requirements.
  2. For certain power rails, ABB (adaptative body bias) must be engaged in:
     • Refer to the device Data Manual for ABB requirements for each OPP
• PCB guidelines:
  The Power Delivery Network should be optimized to match all OPP requirements. All PCB Design requirements for PDN optimization can be found in the Data Manual.
  It is mandatory for the PCB developer to align the PCB with the described guidelines and to meet TI requirements.

REVISIONS IMPACTED

SR 1.0

DRA75xP, DRA74xP, DRA77xP, DRA76xP: 1.0

TDA2Px: 1.0