CRITICALITY

Medium

DESCRIPTION

An enhanced standby behavior is implemented inside DSS to avoid the usage of SW procedure, calculating the optimal DMA thresholds. This enhanced standby behavior allows DSS to go into standby even for cases where the threshold values programmed are non-optimal.

A bug is identified in this implementation, which causes DSS underflows when DSS is in smart-standby mode and when multiple pipelines are enabled.

An additional bit (bit 0) has been added to DISABLE_MSTANDBY_ENHANCEMENT register (physical address: 0x58001858) to enable(0x0)/disable(0x1) the enhanced standby behavior.

WORKAROUND

Setting DISABLE_MSTANDBY_ENHANCEMENT[0] bit to '1' (disables the enhanced standby behavior) and prevents the occurrence of this bug.

REVISIONS IMPACTED

SR 1.0

AM574x: 1.0

DRA75xP, DRA74xP, DRA77xP, DRA76xP: 1.0

TDA2Px: 1.0

AM576x: 1.0