CRITICALITY

Medium

DESCRIPTION

Access to the PCIe slave port that are not 32-bit aligned will result in incorrect mapping to TLP Address and Byte enable fields. Therefore, byte and half-word accesses are not possible to byte offset 0x1, 0x2, or 0x3.

WORKAROUND

To workaround this issue, there are two options:

1. Avoid issuing read accesses to the PCIe slave port that are not 32-bit aligned
2. Set the PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE and PCIE_SS2_AXI2OCP_LEGACY_MODE_ENABLE bits to 0x1 in the CTRL_CORE_SMA_SW_7 Control Module register. This will make all Read TLPs 32-bit aligned with all byte enables set to 1.

REVISIONS IMPACTED

SR 1.0

AM574x: 1.0

DRA75xP, DRA74xP, DRA77xP, DRA76xP: 1.0

TDA2Px: 1.0

AM576x: 1.0