Details

When operating the 2-L SerDes PCIe Reference Clock in Output mode, the RMS jitter of the clock may exceed the PCIe specification limit for the 5.0 GT/s Data Rate.

Workaround

Option 1:

Configure the Reference Clock output in Derived Refclk mode (as opposed to Received Refclk mode) and program the PLL configuration registers as follows:

Internal SSC mode requires no PLL configuration change.

For No SSC mode, the following registers should be written to change the PLL configuration:

• Set cmn_plllc_bwcal_mode0_preg = 0x8706
• Set cmn_plllc_lf_coeff_mode0_preg = 0x2005

Option 2:

Do not operate the PCIe interface at the 5.0 GT/s Data Rate.

Option 3:

Use an external clock source to supply the PCIe Reference Clock to both the Root Complex and End Point Devices of the Link.

Internal Note:

When measuring the Refclk output, the SerDes should be configured in the A2 state to power-down the TX/RX. This is consistent with the test methodology applied to external Refclk generators.