SPRZ455D december 2020 – june 2023 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
ADVANCE INFORMATION
STOG: SRC side write data bus hang when a write command timeout occurs the same cycle as last acceptance on DST side
If a write command times out the same cycle the last write dataphase is accepted on the destination side of the gasket, the gasket's source side will permanently stop accepting write data and won't be able to flush/auto respond properly.
Programming the gasket with low timeout period can result in a system hang due to the time out gasket stop accepting write data.
Software should set a sufficiently large timeout period that well exceeds the longest possible write command burst transmission period. The default timeout period for the gasket is sufficient - 3 x 2^30 cycles.